Pozadis said: "We don't believe there is a fundamental limitation. We believe we can extend this to 3-bits, even 4-bits per cell." He confirmed that the use of iterative programming and coding has implications for slower program and read times. There is also a die area penalty, he said because of the use of reference cells and the need to provide encode/decode hardware.
The PCM test chip was designed and fabricated by scientists and engineers located in Burlington, Vermont; Yorktown Heights, New York and in Zurich.
The paper Drift-tolerant Multilevel Phase-Change Memory by N. Papandreou, H. Pozidis, T. Mittelholzer, G.F. Close, M. Breitwisch, C. Lam and E. Eleftheriou, was presented by Pozidis at the IEEE International Memory Workshop held in May 2011 in Monterey, California.
For further information: www.zurich.ibm.com.