IBM reports drift-tolerant multilevel cell PCM: Page 2 of 2

July 01, 2011 //By Peter Clarke
IBM reports drift-tolerant multilevel cell PCM
Scientists at IBM Research in Zurich, Switzerland, have reported a method to store multiple bits reliably in a phase-change memory cell. The team used four levels (2-bits) per memory cell in a 200 k-cell array implemented in a 90-nm process technology and reported a coding method to overcome the tendency of the material properties to relax over time. The memory cell is of the mushroom type with doped Ge2Sb2Te5 as the phase-change material.
bits per cell with a 1 in 100,000 bit error rate after 37 days at room temperature. This is before the use of conventional error-correction codes that could bring the overall error rate down to levels around 1 in 10^15 or less, which are required for practical memory devices, the authors said in the paper.

Pozadis said: "We don't believe there is a fundamental limitation. We believe we can extend this to 3-bits, even 4-bits per cell." He confirmed that the use of iterative programming and coding has implications for slower program and read times. There is also a die area penalty, he said because of the use of reference cells and the need to provide encode/decode hardware.

The PCM test chip was designed and fabricated by scientists and engineers located in Burlington, Vermont; Yorktown Heights, New York and in Zurich.

The paper Drift-tolerant Multilevel Phase-Change Memory by N. Papandreou, H. Pozidis, T. Mittelholzer, G.F. Close, M. Breitwisch, C. Lam and E. Eleftheriou, was presented by Pozidis at the IEEE International Memory Workshop held in May 2011 in Monterey, California.

For further information:

Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.