While the dimensional scaling of traditional front-end technologies is expected to slow down, the back-end-of-line dimensions keep on scaling to keep up with the required area scaling. For the 3nm logic technology node, M2 interconnect layers with metal pitches as tight as 21nm need to be manufactured while preserving the back-end-of-line’s performance. This implies a tight control of the RC delay, while maintaining good reliability.
Imec proved the reliability of the dual-damascene 21nm metal pitch test vehicle it produced, observing no electromigration failures even after 530 hours at 330°C, while dielectric breakdown (TDDB) measurements demonstrated a time-to-failure greater than 10 years at 100°C.
To pattern the M2 layer, the researchers used a hybrid lithography approach relying on 193nm immersion-based self-aligned quadrupole patterning (SAQP) for printing the lines and trenches, and extreme ultraviolet lithography (EUVL) for printing the block and via structures. The test vehicle implemented a barrier-less ruthenium (Ru) metallization scheme and an insulator with dielectric constant k = 3.0.
First results also demonstrate that the proposed interconnect technology can be improved by adding scaling boosters, including buried power rail, SuperVia, self-aligned blocks, fully self-aligned vias and double self-aligned blocks.
Imec - www.imec-int.com