The two organizations are working on an extreme ultraviolet lithography enabled process to produce a six-transistor SRAM cell with an area of about 0.02 square microns. This would meet or exceed the cell area of the N5 (5nm) technology node but because the transistors are organized vertically with gate all around a pillar would have a much-relaxed pitch of about 50nm
An Steegen, executive vice president of semiconductor technology and systems, said that the vertical gate-all-around SGT-based cells have a 20 to 30 percent reduced area compared to horizontal gate-all-around FETs, while also outperforming these in terms of operating voltage, standby leakage and stability.
"SGTs have all the advantages of horizontal gate-all-around transistors, allowing a near-perfect electrostatic control of the transistor channel," says Professor Masuoka, in a statement issued by IMEC. "But because the channel is a vertical pillar, the concept has the potential for a significant area reduction compared to horizontal nanowire-based transistors."
Unisantis is not so much a startup as long-term research team. It was founded in 2004 to develop three dimensional transistors and was joined by Professor Fujio Masuoka as chief technology officer. Previously Professor Masuoka had spent 23 years at Toshiba Corp. He is credited as the inventor of the flash memory. Since 2007 Unisantis has been working with the Institute of Microelectronics in Singapore on the development of Surrounding Gate Transistors.
IMEC and Unisantis used design process technology co-optimization (DCTO) to develop both the SRAM design with a bit-cell area of 0.0205 square microns, using a minimum pillar pitch
of 50nm. This is 24 percent better than the smallest SRAM designs published to date.
Next: EUV plays its part