RISC-V as an open ISA (Instruction Set Architecture) that allows many approaches to implement a processor core and provides SoC developers with a wide range of sourcing options, including commercial IP suppliers, open-source projects and self-developed in-house cores. In addition, the Open ISA aspect of RISC-V also permits the SoC developer to extend the standard core configurations with optimized custom instructions or extensions. Coupled with this design freedom is the challenge faced by DV engineers on the verification and test plans required for the next generation of domain specific devices.
Working with the Google Cloud Open-Source RISC-V Instruction Stream Generator (https://github.com/google/riscv-dv), the team at Imperas, with assistance from Mentor, developed and enhanced the verification flow to compare the same corner case scenario for the functional behavior of the RTL-under-test, using the Questa platform environment against the golden reference model developed by Imperas.
This reference model, riscvOVPsim, is available for free on GitHub for both academic and commercial users. The latest development has been to expand the coverage analysis features to assist the DV engineers as they develop comprehensive test and verification plans for a new core implementation, custom extension, or initial assessment of a core prior to SoC integration.
“RISC-V offers processor designers and SoC developers flexibility in design configuration and optimization for the next generation of domain specific devices,” said Neil Hand, director of marketing, Design Verification Technology Division at Mentor, a Siemens business. “Our collaboration with Imperas and the golden reference simulator coupled with the Google Cloud Open-Source RISC-V ISG can provide DV engineers with a flow that now includes the critical coverage analysis required to support the latest verification methodologies.”