Improved Inter Integrated Circuit (I3C) IP core

December 05, 2017 // By Julien Happich
Digital Core Design has released the DI3CM-FIFO IP core, incorporating all features required by the latest MIPI I3C specification.

The I 3C (Improved Inter Integrated Circuit) is the next generation of the I 2C, offering major improvements in terms of use, power consumption and performance. The Core uses just two pins and consumes a fraction of energy, reducing cost and complexity while allowing multiple sensors from different vendors to be easily interfaced to a controller or application processor. The DI3CM-FIFO offers a flexible multi-drop interface between the host processor and peripheral sensors to support the growing usage of sensors in embedded systems.

The I 3C interface uses an I 2C-like interface with data line (SDA) and clock line (SCL). The open drain SDA line allows for slaves to take control of the data bus and initiate interrupts. The push-pull SCL line is used by the master to clock the communication bus up to 12.5MHz. The master can dynamically assign 7-bit addresses to all I3C devices while supporting the static addresses of legacy I2C devices. This ensures full compatibility between MIPI I3C and I 2C. The Core represents a shift in power performance while providing greater than an order of magnitude improvement in speed over I 2C. I 3C offers four data transfer modes that, on maximum base clock of 12.5MHz, provide a raw bitrate of 12.5 Mbps in the baseline SDR default mode, and 25, 27.5 and 39.5 Mbps, respectively in the HDR modes. After excluding transaction control bytes, the effective data bitrates achieved in each mode are 11.1, 20, 23.5 and 33.3 Mbps, respectively, protected by I 3C's basic error detection mechanisms.

Digital Core Design -


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