The result is a new IP core dubbed logiHSSL that enables high-speed communication between Infineon’s AURIX TC2xx and TC3xx microcontrollers and Xilinx’ SoC, MPSoC and FPGA devices via the Infineon High Speed Serial Link (HSSL). This serial link supports baudrates of up to 320 Mbaud at a net payload data-rate of up to 84%. The HSSL is an Infineon native interface, low-cost in regards to pin-count as it requires only five pins – two LVDS with two pins each and one clk pin. So far, the HSSL interface is used to exchange data between AURIX devices and customer ASICs for performance or functional extension. Now, the new IP core will allow system developers to combine safety and security provided by AURIX with the wide range of functional possibilities brought to the table by the Xilinx devices. Linked devices can access and control each other’s internal and connected resources through the HSSL.
To support development activities the partners are offering a starter kit . It includes a Xilinx evaluation kit , an Infineon AURIX evaluation board and a Xylon FMC board. Kit deliverables include the reference design with the test software application, Xylon’s logicBRICKS evaluation licenses, documentation and technical support. The new IP core and the development kit will be available starting in March 2019.
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