Infrastructure processors support up to 36 Arm v8 cores

March 03, 2020 //By Julien Happich
Marvell’s Octeon TX2 family of infrastructure processors targets a wide variety of wired and wireless networking equipment.

The infrastructure processor family now combines up to 36 cores, based on the Arm v8-A architecture with configurable and programmable hardware accelerator blocks, connected by Marvell’s highly scalable coherent interconnect. Compared to architectures that process data solely on CPU cores, these accelerator blocks – which include security, packet processing, and traffic management functions – are able to meet the most demanding performance and power requirements.  The integrated hardware accelerators offer 2.5x improvement over the company’s previous generation of Octeon processors with scalable throughput ranging from 10Gbps to over 200 Gbps. What’s more, the Octeon platform is enabled by a mature and widely deployed SDK, supported by robust software ecosystems consisting of both open source and commercial offerings. The platform includes firmware, Linux OS and multiple distributions, virtualization, containers, data plane development kit (DPDK), protocol stacks, infrastructure management and orchestration like OpenStack and Kubernetes, and virtual network functions (VNFs).  In addition, Marvell supports a full routing stack including TCP, SSL, and IPSEC support and DPDK support for L2/L3 forwarding and IPSEC.

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