Intel taps Dutch team for second generation quantum controller

December 08, 2020 // By Rich Pell
Intel debuts 2nd-gen cryogenic quantum computing control chip
Intel has unveiled Horse Ridge II, its second-generation cryogenic control chip for quantum computing, continuing its work with the QuTech team at TU Delft.

The second generation of controller for quantum computers can fit inside the cryogenic fridge includes the ability to manipulate and read qubit states and control the potential of several gates required to entangle multiple qubits.

“With Horse Ridge II, Intel continues to lead innovation in the field of quantum cryogenic controls, drawing from our deep interdisciplinary expertise bench across the Integrated Circuit design, Labs and Technology Development teams," said Jim Clarke, director of Quantum Hardware for the Components Research Group at Intel. "We believe that increasing the number of qubits without addressing the resulting wiring complexities is akin to owning a sports car, but constantly being stuck in traffic. Horse Ridge II further streamlines quantum circuit controls, and we expect this progress to deliver increased fidelity and decreased power output, bringing us one step closer toward the development of a 'traffic-free' integrated quantum circuit.”

The first chip was designed to address the current approach to today's early quantum systems, which use room-temperature electronics with many coaxial cables that are routed to the qubit chip inside a the dilution refrigerator. This approach limits the scalability to a large number of qubits due to form factor, cost, power consumption, and thermal load to the fridge.

Intel has worked with TU Delft in the Netherlands on the technology, aiming to get the technology down to the point where the controller can be co-packaged with the qubits. That would dramatically reduce the size of quantum computers. The Dutch team worked on the original 128 qubit Horse Ridge controller which used a 180Kbit SRAM for envelope storage, a digital polar modulator, a 1-GSa/s 10-bit I/Q DAC and a wideband RF front-end. The team is now looking at higher perfomrance RF design and ways to get the temperature down from 3K to under 1.5K. 

This design simplified the interconnect and used signal processing techniques to accelerate setup time, improve qubit performance, and


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