JTAG/Boundary-scan - the development of standards

March 12, 2015 //By Peter van den Eijnden
JTAG/Boundary-scan - the development of standards
Prompted by a change in device packaging almost 30 years ago (from through hole to surface mount) a group of like-minded test engineers met to consider the impact that these parts would have on testing their forthcoming assemblies – they called themselves JTAG or Joint Test Action Group and were formed from representatives of Philips, BT, TI, IBM, DEC and others.

In most cases PCB testing at that time (mid 1980s) had been accomplished using ICT (In-Circuit Testers) for individual component and PCB testing, or functional testers that could mimic the environment of the UUT (Unit Under Test) to send/receive stimulus and response signals. The work of the JTAG committee however would change the test landscape dramatically.

The fruits of their labour was the now familiar 'Test Access Port and Boundary-scan Architecture' (aka IEEE 1149.1), and it describes how an embedded serial scan register can access digital signal pins of its host device to either capture an input signal or propagate an output signal through the pin of the device while isolating its regular function.

By applying test patterns across interconnections between devices, assemblies could be tested for open circuits and shorts. Soon after tests were being developed that could stimulate and check the interconnects to RAMs, Flash and other logic parts. A few years after that the JTAG TAP was being used access for configuring/programming PLDs FPGAs and microcontrollers.

 

Fast forward 30 years and you can see that JTAG/IEEE 1149.1 usage for both testing and programming has become mainstream, being used extensively in testing of PCB assemblies within Defense, Aerospace, Telecoms Automotive, and Industrial sectors. Yet the need to pre-empt future test issues remains a constant and current wisdom suggests more ‘at-speed’ testing through use of [device] embedded instruments is to be encouraged.

The most recent major update to standard 1149.1 came in 2013 with a sizable addendum to the original work which came about following a period of intense activity around 2010, with two separate groups proposing similar updates to the existing 1149.1 standard, which was by then 20 years old. 

As well as 1149.1 2013 there also existed a group working on IEEE 1687. Both groups had identified deficiencies in the existing standard and both groups have addressed these through the introduction of more ‘dynamic’ IC infrastructures.

In the case of 1149.1 2013 the driver for the changes was to standardise some of the design practices that IC vendors had introduced on a unilateral basis, such as initialisation protocols, individual device id codes and power management scenarios. While in the case of 1687 the main driver was to improve board-level ‘testability’ through the greater use of embedded test cores (BIST IP) accessed via an extended standardised infrastructure.

The now-ratified extension to 1149.1 has more than doubled the size of the descriptive document to 444 pages and includes the syntax of a new procedural description language (PDL) that is used to define the usage of the dynamic register segmentation and device IP hierarchy for a given application. IEEE 1687 meanwhile also features PDL, however there is only a basic level of compatibility between the two PDLs – apparently due to the vastly different focus of each new standard!


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