JTAG/Boundary-scan - the development of standards : Page 2 of 2

March 12, 2015 //By Peter van den Eijnden
JTAG/Boundary-scan - the development of standards
Prompted by a change in device packaging almost 30 years ago (from through hole to surface mount) a group of like-minded test engineers met to consider the impact that these parts would have on testing their forthcoming assemblies – they called themselves JTAG or Joint Test Action Group and were formed from representatives of Philips, BT, TI, IBM, DEC and others.

PDL is designed to document the procedures for stimulating and observing test data register fields for 1149.1-2013 and in P1687, the procedures for stimulating and observing data to an instrument. Not much of a difference except that in P1687 a second language is required to describe the [embedded instrument] access networks – ICL (Instrument Control Language) while in 1149.1-2003 the access network descriptions are embedded in an extended BSDL model. For complex networks that make extensive use of embedded instruments P1687s ICL is claimed to be better suited.

See below redrawn block diagrams of the two ‘competing’ standards so the differences can be made clear.

The argument for the continued development of standards are clear. Chiefly these are a) to keep the technology relevant to today’s designs and b) to ease the task of tool vendors who rely on standard techniques to achieve maximum levels of automation in application generation. c) expand the market potential of a given methodology.

What else is in store for the future? Well I think we can expect expansion of the features for enabling JTAG to go in two, more or less opposite, directions.

1) More embedded testing at device level (as per IEEE 1687 and IEEE 1149.7) and

2) Extended infrastructures for system-level access and test as espoused by the SJTAG committee (see www.sjtag.org) who’s purpose is stated on the web-site as follows – ‘...to provide an extension of the IEEE 1149.1 standard specifically aimed at enabling the configuration, control, management, and representation of the communications required at the hierarchical system and board levels to perform operations on the IEEE 1149.1 Test Access Port (TAP) of one or more devices or device cores, in a uniform and transportable way across all system modules’.

However, it is a slow process and only time will tell if the ‘standard makers’ can offer a needed system that is both timely and profitable for the silicon vendors to implement. In the world of test standards much good work has now been put into everyday use while other developments have withered on the vine. There has always been a difficult balancing act in developing viable test methods that can be standardised and used profitably

About the author:

Peter van den Eijnden is Managing Director of JTAG Technologies - www.jtag.com


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