To obtain high-performance top FETs, low gate access resistance was achieved using UV nano-second laser recrystallization of in-situ doped amorphous silicon. Full 500°C selective silicon-epitaxy process was demonstrated with an advanced LT surface preparation and a combination of dry-and-wet etch preparation. Epitaxial growth was demonstrated with the cyclic use of a new silicon precursor and dichlorine Cl2 etching. At the same time, the project paved the way to manufacturability of 3D sequential integration including iBEOL with standard ULK and Cu-metal lines.
A bevel-edge contamination containment strategy comprised of three steps (bevel etch, decontamination, encapsulation) enabled reintroducing wafers in an FEOL environment following the BEOL process. In addition, the project also demonstrated for the first time the stability of line-to-line breakdown voltage for interconnections submitted to 500°C. The work also demonstrated a Smart Cut transfer of a crystalline silicon layer on a processed bottom level of FD-SOI CMOS devices, as an alternative to the SOI bonding-and-etch back process scheme for top channel fabrication.
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