A low power ECP5 FPGA from Lattice provides processing for the AI or smart vision workload and serves as the memory controller for Etron’s high performance RPC DRAM. The reference design reduces power consumption, overall design size, and data latency by allowing developers to store data used in AI and smart vision applications locally instead of using larger, external memory cards. As implemented on the reference design’s PCB, the Lattice/Etron solution uses 15% less power than a system using standard DDR3 DRAM, yet has an overall design footprint smaller than the 9x13mm BGA package used by a standard DDR3 DRAM chip. The reference design includes software development tools, featuring a GUI-based memory code generator tool and a Verilog simulation model. Application demonstrations featuring the Lattice sensAI solutions stack and the RPC DRAM memory controller reference design will be available from Etron in the third quarter of this year.
Etron America - https://etronamerica.com
Lattice Semiconductor - www.latticesemi.com