Marvell is looking to shake up the custom ASIC chip market with a new 5nm offering for 5G carriers, cloud data centres, enterprise and automotive applications.
Leading edge custom ASIC designs are expensive, not just from the cost of mask sets but the development of the additional IP that is needed in chips that can have billions of transistors.
Marvell has a wide range of IP blocks that are already used in its standard products. IBM's former ASIC division was acquired from Global Foundries last year and has access to all these blocks and experience with over 2,000 designs. These IP blocks include ARM-based processors, embedded memories, high-speed SerDes, networking, security and a wide range of storage controller and accelerators in 5nm and beyond.
The division has access to the Global Foundries but can also use other foundries. However chip designs at 5nm and beyond cost up to a third more than 7nm from the increase in mask costs: CHIP DESIGN IS ONE THIRD MORE COSTLY THAN AT 7nm
Traditionally, data infrastructure manufacturers and cloud data centre operators have had to choose between securing standard products or a full custom silicon solution designed in-house, while developing or licensing foundational IP as needed. For the first time Marvell is offering full access to its broad and growing portfolio of industry-leading data infrastructure standard product IP and technologies for integration into custom ASIC designs at 5nm and below as well as 13 other process technology nodes.
These markets are growing fast as data centres expand and 5G networks roll out.
“The future of compute requires scalable and highly optimized solutions that can power the data centre all the way to the network edge,” said Mohamed Awad, vice president of Marketing, Infrastructure Line of Business at ARM, which is currently up for sale: CADENCE COULD BE GOOD FIT AS ARM IS SHOPPED AROUND. However Marvell has an architecure license that allows it to develop and maintain its own processor cores, which is a key advantage for the ASIC business.