Mentor has joined STMicroelectronics in the European Nano2022 project to accelerate the characterisation of standard cells, I/Os and memories.
Characterizing silicon platforms with hundreds of cells and several hundred process, voltage and temperature (PVT) variables can consume thousands of CPUs for weeks, running millions of SPICE simulations and generating billions and even trillions of data points. This bottleneck is a productivity drain for the broader semiconductor industry.
New reinforcement-learning techniques are planned during the program to speed up platform characterization, including process technologies under 10nm.
“Characterisation of standard cell libraries is really important for us,” said Cyril Colin-Madan, deputy director of Technology and Design Platforms for STMicroelectronics. “After highly successful collaborations under the Nano 2012 and Nano 2017 programs, we aim to further advance the state of microelectronics design and manufacturing in Europe under Nano 2022,” he said.
“We are focussed on an area, characterisation of standard cell libraries, that has a large impact on the design flow,” said Jean Marc Talbot, Senior Engineering Director DSM/AMS at Mentor. “Library characterisation is at the boundary of the production of IP and the use of the libraries in the physical design flow for synthesis and timing analysis. This is a growing bottleneck for advanced nodes which is why we decided to focus on this.”
“Libraries have thousands of cells with different voltages, hundreds of different voltage and temperature corners. We are talking about millions of simulations and thousands of files so we are in the world of big data and the associated challenges,” he said.
A simple computation for characterisation for example for 500 corners for 5000 standard cells requires a spice simulation for each item so this needs 14 billion simulations with thousands of CPUs for several weeks for a 28nm process and it is getting worse with statistical simulations.