The new SerDes chipset also enables designs that can receive 2 different video inputs simultaneously, as well as applications that can copy and distribute (simultaneously replicate) 1 video stream into 2. THCV241A serializes up to 4 lanes of MIPI CSI-2 signals and converts it into 1 or 2 lanes of V-by-One HS (developed and owned by THine). V-by-One HS technology supports up to 4 Gbps per lane which is robust enough to extend the transmission of 1080p60 2Mpixel uncompressed video for greater than 15 meters with typical cables. THCV241A’s 2 lanes of V-by-One HS supports up to an 8 Gbps data rate with the capability to use the second V-by-One HS lane to support data copy and distribution (replication) applications. The THCV242 chip deserializes up to 2 V-by-One HS lanes back to the original MIPI CSI-2 signal.
The chipset supports “Sub-Link” that aggregates bidirectional low speed signals, such as GPIO. The separation of high speed signal path, V-by-One HS, and Sub-Link enables easy debugging and gives more choices for physical harnesses including the utilization of Keyssa’s contactless connection for systems benefiting from or requiring a ruggedized, low latency, detachable camera.
Mirrored video signal redundancy supported by this chipset can be used for troubleshooting system problems or for applications such as agricultural robotics and 3D surgical equipment which require a secondary application processor that is distant from the source video camera.
THine Electronics - www.thine.co.jp