MIPI CSI-2 receiver IP core is configurable up to 4 data lanes

October 04, 2019 //By Julien Happich
MIPI
Sensor to Image’s MIPI CSI-2 receiver IP core provides a solution for decoding video streams from CSI-2 sensors in a Xilinx FPGA.

It uses a companion IP core, provided by Xilinx, implementing the MIPI D-PHY physical interface. The D-PHY receiver is connected to the CSI-2 sensor using the PHY-Protocol Interface (PPI). The core is delivered with a complete reference design for S2I’s MVDK with a Zynq Ultrascale+ FPGA and an IMX274 MIPI FMC module. Since the physical interface is abstracted by the Xilinx D-PHY core, it is easy to port the design to other FPGA platforms like for example the 7 series Xilinx FPGAs. The core accepts RAW8, RAW10, RAW12, RAW14, and RAW16 standard MIPI data types, it is configurable to 1, 2 or 4 data lanes with any lane rate. The lane management together with the packet engine receive parallel byte lanes, extract control information, implement lane alignment and byte reordering, and finally provide aligned payload byte streams. The pixel unpacker extracts pixel data types out of these byte streams. The output pixel clock adjustment converts the pixel stream into the output clock domain. The control interface contains a set of control and status registers accessible by a CPU using the AXI4-Lite slave interface. The MIPI CSI-2 Receiver IP Core is delivered as encrypted VHDL. It is optionally available as VHDL source code.

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