“Our customers are asking for FPGAs with MIPI D-PHY capability to solve increasingly difficult video interface problems. Too often, they reach barriers with solutions that miss the mark on power efficiency, size and performance,” said Tom Watzka, product marketing manager at Lattice Semiconductor. “For more than a year, Lattice’s CrossLink devices and its portfolio of IP cores have delivered the tools needed to overcome these challenges. These new IP cores add to an already robust suite of tools to support quickly evolving intelligence at the edge applications.”
Announced in May 2016, the CrossLink product was designed to address barriers faced by the increasingly complex and dynamic video market. The new CrossLink modular IP cores include a CSI-2/DSI D-PHY receiver that converts MIPI CSI-2/DSI data streams to parallel data, a CSI-2/DSI D-PHY transmitter that converts parallel formatted data streams to MIPI CSI-2/DSI, an FPD-LINK receiver that converts FPD-LINK video streams to pixel clock domain, an FPD-LINK transmitter that converts pixel data streams to an FPD-LINK video stream, a subLVDS image sensor receiver that converts SubLVDS image sensor video stream to pixel clock domain, a pixel to byte converter that converts pixel format data to parallel byte format for D-PHY transmitter and a byte to pixel converter that converts parallel byte format from a D-PHY receiver into pixel format.
In addition, Lattice has included a 1:2 MIPI DSI display interface bandwidth reducer , which utilizes select modular IP cores above to bridge an input video stream into two streams or one lower resolution stream. CrossLink evaluation boards with the new IP cores are available now from Lattice and its distributors.
Lattice Semiconductor - www.latticesemi.com