Multi-bit memory chip stacks on top of CMOS for edge-AI

February 22, 2019 //By Julien Happich
Multi-bit memory chip stacks on top of CMOS for edge-AI
In a joint paper titled, “A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques” presented at the International Solid-State Circuits Conference (ISSCC) 2019 in San Francisco, researchers from CEA-Leti and Stanford University disclosed a proof-of-concept multi-bit chip said to overcome NVM’s read/write, latency and integration challenges.

As a world’s first, the researchers integrated multiple-bit non-volatile memory (NVM) Resistive RAM (RRAM) technology with silicon computing units, as well as new memory resiliency features said to provide 2.3-times the capacity of existing RRAM.

Target applications include energy-efficient, smart-sensor nodes to support artificial intelligence on the Internet of Things, or “edge AI”.

The proof-of-concept chip has been validated for a wide variety of applications such as machine learning, control and security. Designed by a Stanford team led by Professors Subhasish Mitra and H.-S. Philip Wong and realized in CEA-Leti’s cleanroom in Grenoble, France, the chip monolithically integrates two heterogeneous technologies: 18 kilobytes (KB) of on-chip RRAM on top of commercial 130nm silicon CMOS with a 16-bit general-purpose microcontroller core with 8KB of SRAM.

The new chip is reported to deliver 10-times better energy efficiency (at similar speed) versus standard embedded FLASH, thanks to its low operation energy, as well as ultra-fast and energy-efficient transitions from on mode to off mode and vice versa.


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