Multi-bit memory chip stacks on top of CMOS for edge-AI: Page 2 of 2

February 22, 2019 //By Julien Happich
Multi-bit memory chip stacks on top of CMOS for edge-AI
In a joint paper titled, “A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques” presented at the International Solid-State Circuits Conference (ISSCC) 2019 in San Francisco, researchers from CEA-Leti and Stanford University disclosed a proof-of-concept multi-bit chip said to overcome NVM’s read/write, latency and integration challenges.

Non-volatility enables memories to retain data when power is off, an essential on-chip memory characteristic for edge nodes that must be able to turn themselves off. The 2.3 bits/cell RRAM enables higher memory density and was tested to yield better application results, such as a 2.3x increase in neural network inference accuracy, compared to a 1-bit/cell equivalent memory.

The CEA-Leti and Stanford team also created a new technique called ENDURER that overcomes the typical write failures of NVM technologies, giving the chip a 10-year functional lifetime when continuously running inference with the Modified National Institute of Standards and Technology (MNIST) database.

Mitra said the chip demonstrates several industry firsts for RRAM technology. These include new algorithms that achieve multiple bits-per-cell RRAM at the full memory level, new techniques that exploit RRAM features as well as application characteristics to demonstrate the effectiveness of multiple bits-per-cell RRAM at the computing system level, and new resilience techniques that achieve a useful lifetime for RRAM-based computing systems.

 CEA-Leti -

Stanford University -

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