Nanium takes wafer-level packaging to XXL

September 25, 2014 // By Julien Happich
Nanium takes wafer-level packaging to XXL
Nanium S.A. has unveiled what the company believes is the industry's largest Wafer-Level Chip Scale Package (WLCSP), a 25x23mm packaging solution produced in volume on 300mm wafers.

Entirely developed in-house for Custom Silicon Solutions (CSS), a California-based provider of complex mixed-signal ASIC solutions, the customized Fan-In Wafer-Level Packaging/ WLCSP solution is nine times larger in area than the industry standard WLCSPs, typically measuring up to 8x8mm.

“After completing a very successful high volume run of a 65nm product in eWLB at NANIUM, we approached them with our next 28nm WLCSP requirements. The first article worked as promised and enabled CSS to get to market quickly with an ASIC unprecedented in thermal and computational performance”, said Mike McDaid, Director of Sales at CSS in a statement.

“No other package solution in existence would have achieved the low lead resistance and high reliability we demanded. This ASIC in Nanium’s WLCSP establishes a new world class of integration, beyond VLSI-SOC (Very Large Scale Integration System-on-Chip). The final product is just about the maximum reticle size allowed and consumes hundreds of Watts!” McDaid added.

The wafers with the high-performance digital chips are produced with 28nm CMOS technology and contain over 5.5 billion transistors, one of the largest transistor-count chip produced by Global Foundries. Once produced in Dresden, Germany, wafers are sent to Nanium for packaging.

The WLCSP solution developed by NANIUM relies on a high count of 1,188 solder balls at a wide BGA pitch of 0.7mm. It has successfully passed more than 400 temperature cycles on board.

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Related articles:

Sensor footprint evolution: Does size matter?

Nanium to offer Fan-In wafer-level packaging in volume on 300mm wafers

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