Based on an enhanced version its NFP-5000 network flow processor, implemented in 28nm CMOS, the resulting card with 2Gbytes of on-card DRAM reduces application tail latency by up to 4x.
The on-chip cryptography relieves the host of this burden and supports Transport Layer Security (TLS/SSL) at line-rate and up to two million sessions per SmartNIC.
Dynamic eBPF-based programming and hardware acceleration enables scaling of networking workloads across multiple host CPU cores. The solution also enhances security and data center efficiencies by offloading TLS, used for encryption and authentication of applications that require data to be securely exchanged over a network.
“Securing user data in Web 2.0 applications and preventing malicious attacks such as BGP hijacking as experienced recently in hyperscale operator infrastructures are critical needs that have exacerbated significantly in recent years,” said Sujal Das, chief marketing and strategy officer at Netronome, in a statement.
Agilio CX 50GbE SmartNICs in OCP Mezzanine 2.0 form factor are sampling today and include the generally available NFP-5000 silicon. The production version of the board and software is expected in the second half of 2019.
The boards are expected to be priced at less than $1,000 per board.
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