Why this sudden increase in hardware-emulation deployment within the design-verification flow?
Hardware emulators are specialized computing engines designed to perform specific tasks, including the functional verification of semiconductor designs and associated verification challenges. They do so at speeds unmet by any software-based verification engine with no penalty in verification accuracy.
However, not all emulators are created equal. Currently, the major hardware-emulation suppliers deliver three different hardware-emulation technologies, architectures, and implementations, making any “apples-to-apples” comparison rather difficult (see figure 1).
A case in point is the parameter called clock frequency. A straight comparison may lead to a wrong conclusion if not properly defined as shown below. In general, hardware-emulation performance is measured by speed, throughput, and latency, three parameters often poorly understood or not grasped at all. Let’s discuss them in detail.
Emulation clock versus design clock
Speed or speed of execution relates to the emulator’s clock frequency. While it’s true that the higher the clock frequency, the faster the execution, the reality is that no two emulators handle clocks in the same way.
Any modern system-on-chip (SoC) design includes a variety of clocks of different frequencies, one being the fastest design clock. It would be reasonable to connect the fastest design clock to the emulator clock. Unfortunately, this is not so.