Notes on real-time computing architectures

May 17, 2016 // By Dennis Feucht
Dennis Feucht
Dennis Feucht discusses different styles of microcontroller architecture and the programming languages they support.

Real-time analog-oriented systems often have embedded microcontrollers (MCUs), if not DSPs or some synergism of the two. Various MCU architectures can be applied to real-time, embedded applications in instrumentation, power conversion, and motion control. This article surveys some design features and tradeoffs of μC architectural types applicable to analog applications.

Memory-Based Computing

The early generations of MCUs were based on architectures with few registers. Their instruction sets made up for this by including addressing modes that eased access to the right memory locations. For instance, the 8-bit 6502, used in the Apple II computer and many Japanese-made VCRs, has one accumulator register, A, and two index registers, X and Y. With Y, it is possible to do table addressing with the indirect, indexed address mode.

For instance, a table-driven step-motor could be advanced by driving its four power switches (for the +/-A and +/-B windings) by incrementing through the table and rolling over to the other end of it. The direction of the motor depends on which direction the program advances through the table. The indirect, indexed addressing mode makes it possible to retrieve in one instruction from memory the switch states for a given step.

With powerful addressing modes, this architecture might be well-suited for real-time control, and in some ways it is. The minimalist design of the 6502 (having 7000 transistors), along with its deterministic instruction pipelining, results in an instruction set in which many of the instructions are only two machine cycles. It in part inspired the design of the increasingly popular, though well-seasoned, ARM (originally Advanced RISC Machine) architecture.

Register-based computing

Reduced-instruction-set computing (RISC) architecture has caught on as a serious challenger to memory-based architectures with their complex-instruction-set computing. The “complex” aspect is the aforementioned addressing modes, which reduce the number of instructions required to access memory but at the expense of more computing cycles required to compute the addresses. The idea emerged

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