Researchers at the Max Planck Institute of Microstructure Physics and Semron in Dresden, Germany, have developed the technique which can easily be implemented using conventional silicon manufacturing processes and systems, paving the way for rapid commercialization.
One approach to reducing the power consumption of deep learning systems is to use in-memory computing where the multiplication and accumulation operation (MAC) is carried out within the memory itself. One common approach is to use analog resistive memory devices, such as memristors or phase-change memory, where the multiplication is carried out by Ohm´s law and the accumulation by Kirchhoff´s current law.
However capacitive devices have a higher signal-to-noise ratio, and the researchers developed a charge shielding layer, which can either transmit or shield an electric field by applying an external voltage to a doped junction or by the influence of a non-volatile ferroelectric memory in an upper dielectric layer.
This allowed them to build a crossbar array of capacitive memory devices to enable highly parallel vector-matrix multiplications.
The researchers fabricated a prototype crossbar array with 156 memory cells and successfully implemented a 5x5 image recognition algorithm for classification of the letters M, P and I. A high dynamic range of 1:1478 and analog programming capabilities were shown for single devices.
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“All previous capacitive approaches suffer either from impractical fabrication or from low precision,” said Kai-Uwe Demasius, CTO of Semron.
Detailed simulations showed a good match between the experimental and simulated results, with scalability demonstrated for devices as small as 45 nm in size.
Using a capacitive memory allowed the use of adiabatic charging to thereby realize an energy efficiency that exceeds 3,500 TOPS/W with 6-8 bit precision. For an algorithm to detect a handwritten digit, an energy efficiency of 29,600 TOPS/W was obtained, which