Pre-silicon prototyping solution for SoC & ASIC designers

September 10, 2019 //By Julien Happich
A provider of mixed HDL language simulation and hardware-assisted verification solutions for FPGA, ASIC and SoC designs, Aldec has enhanced its HES Proto-AXI software to offer even greater support to designers using the company’s HES pre-silicon prototyping solution.

The enhancements include support for QEMU (the open source machine emulator and virtualizer) and SystemC TLM version 2.0, plus resources that increase the interoperability of HES Proto-AXI with third party tools.

“The addition of QEMU is of immense benefit,” says Zibi Zalewski, General Manager of Aldec’s Hardware Division. “QEMU emulates a CPU subsystem which can generate AXI transactions for the design or algorithm kernel running in a HES board. The interface can also be used during simulation when the application is under development.”

Of equal benefit is support for the latest version of SystemC TLM. This transaction-level modelling (TLM) interface is commonly adopted as the interconnect standard in Virtual Platforms that are used to model CPU subsystems for architecture exploration and early software development. This feature allows for the linking of design components, running on a HES board and connected with HES Proto AXI infrastructure, with the CPU sub-system running the Virtual Platform.

The latest version of HES Proto-AXI also features Xilinx Vivado and Microsoft Visual C++ support. HES is a SoC/ASIC pre-silicon prototyping solution for hardware verification and software validation teams. It is also a high-performance computing (HPC) platform for algorithms acceleration. The boards are based on the largest Virtex-7 and Virtex UltraScale FPGAs, appear in single or multi-FPGA configurations, and can be interconnected on a backplane board to provide for up to 663 Million ASIC gates.

Aldec -

Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.