The £6.5m (€7.6m) CryConsortium project. led by memory IP devleoper SureCore, aims to reduce the constraints associated with interconnects in cryogenic systems to enable efficient scaling of qubits. The key challenge for these platforms is the lack of availability of suitable control circuitry capable of operating at the cryogenic temperatures needed to manage qubits operation.
Currently the control circuitry is located remotely from the qubits and connected by expensive and bulky cabling in order to avoid the temperature extremes needed by the qubits. The amount of cabling required for all the qubits presents a fundamental barrier to QC scaling aside from the inherent latency impact.
The obvious solution is to co-locate the control electronics with the qubits in the cryostat but this means that both must be kept at ultra-low temperatures; in some implementations down to near absolute zero. However, not only is space extremely limited in the cryostat, necessitating the miniaturisation of the control circuity, but the modern semiconductors that make up these chips are only qualified to work down to -40° C. As the temperature is reduced close to absolute zero, the operating characteristics of the transistors change markedly.
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The project aims to understand and model this change in behaviour and then design a portfolio of CryoCMOS IP to enable the creation of custom chips that can interface to the qubits at cryogenic temperatures and support controller functionality.
“We are proud to lead this project. It is vital to the success of this project that the Cryo-CMOS produces as little heat as possible. Heat comes from the power usage in the chip and we have perfected several ways to cut power consumption in the memory components of chips by up to 50%. As these QCs will be doing intense computations, there will be huge demand for memory so the savings in power and hence heat will be critical to the operational success of the cryo control chips,” said Paul Wells, CEO of sureCore.
The consortium consists of the complete ecosystem of companies to provide the core competencies required to rapidly develop this cryo-tolerant IP. This would then be available under license for companies to create their own Cryo-CMOS chip designs.
The first step is accurately modelling how transistors work at these temperatures. This is being done by SemiWise and the QC research group at the University of Glasgow. Synopsys uses the data generated to refine its TCAD tools. A combination of measurements and simulation data will be used by SemiWise to re-centre the foundry PDK for cryogenic temperatures and to enable the cryogenic circuit design.
“SemiWise is delighted to pay a key role in this project, delivering the cryogenic version of the foundry PDK and enabling the SRAM and, indeed, general circuit design at cryogenic temperatures. We believe that this will deliver a significant competitive advantage to the rest of the consortium partners,” said Professor Asen Asenov, CEO of SmiWise.
As memory plays a key role in the electronics, this aspect is handled by sureCore, which is leading the project and whose expertise at keeping chip power consumption low is vital to ensure that waste heat is kept to a minimum so it does not heat the chamber. Chamber expertise is provided by Oxford Instruments which manufactures cryogenic systems.
Lastly, Universal Quantum and SEEQC represent end user needs and will determine what IP blocks the project will need to create for the Cryo-CMOS chips. Test chips will be characterised at the cryo temperatures to further refine and validate the models and IP.
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