Researchers shrink RF transformers, roll them up on top of CMOS

May 17, 2018 //By Julien Happich
Researchers shrink RF transformers, roll them up on top of CMOS
Doing away with the complex miniaturized coil manufacturing techniques used for embedding on-chip RF transformers with limited performance planar or multi-layered coils, researchers from the University of Illinois have turned simple 2D planar loop designs into closely inductively coupled 3D coils.

To create the micrometre-sized rolled-up RF transformers they describe in a paper titled "Three-dimensional radio-frequency transformers based on a self-rolled-up membrane platform" published in Nature Electronics, the researchers rely on silicon nitride's intrinsic mechanical properties and built-in stress upon deposition, which when released from a sacrificial layer, rolls-up naturally to ease the strains.

A photomicrograph of three 50-micron diameter rolled
transformers developed by Illinois professor Xiuling Li’s
team. Image courtesy Wen Huang.

Interestingly, the SiNx-based self-rolled-up membrane (S-RUM) nanotechnology platform described in the paper allows designers to completely parameterize the final 3D configuration of the primary and secondary windings of an RF transformer, all from an original 2D layout lending itself to conventional photolithography manufacturing processes.

Schematic of the rolled-up 3D transformer
structure from the planar layout with parasitic
parameters and ‘coil cells’ labelled.

Through theoretical modelling of the deposited strained bilayer SiNx nanomembrane used as a substrate for 2D conductive patterns, the scientists are able to calculate the precise dimensions of the finished rolled-up membranes and the electrical performance of the resulting air-core RF transformer they want to design. This includes the inner diameter and the number of turns of the primary and secondary coils according to the turns ratio and inductance requirements of the end design. Since the membrane structure of S-RUM transformers can include multiple layers of dielectric and conductive thin films, each layer with its own built-up stress, self-coiling results from the stress imbalance from the whole stack.

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