A RISC-V fully European platform for space
Combining a multicore system-on-chip by leading space solutions provider Cobham Gaisler with fentISS’ space-qualified XtratuM hypervisor, De-RISC will create a market-ready platform to power future space and aeronautical applications with made-in-Europe technology.
Thanks to Barcelona Supercomputing Center’s proven multicore interference mitigation techniques, the platform will offer high-performance operation with dramatically reduced interference. Meanwhile, Thales, one of the strongest players in the space and aviation market worldwide, will test the platform on real aerospace applications.
‘With the first RISC-V based, fully European platform for space, De-RISC will guarantee access to made-in-Europe technology for aerospace applications, thus contributing to the “Technologies for European non-dependence and competitiveness” programme in these strategic markets,’ explains Paco Gomez Molinero, chief executive officer of fentISS and coordinator of the De-RISC project.
The use of RISC-V will also help to future-proof the platform, thanks to an ever-increasing support for the open-source instruction set architecture (ISA), at a time when the proprietary PowerPC and SPARC architectures traditionally used in aviation and space systems are experiencing a loss of momentum. As a result, the space industry is not able to leverage software from the commercial domains, fuelling a need to shift to architectures present in higher volume commercial markets. The final platform will be portable to other architectures, and it will also provide superior fault tolerance.
De-RISC is a 30-month Innovation Action partially funded by the European Commission, which launched with a budget of € 3,444,625.
Related articles:
European Processor Initiative: roadmap update
X-FAB Silicon Foundries tapes-out open-source RISC-V MCU
C/C++ compiler and debugger toolchain supports RISC-V cores
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
