RISC-V reference simulator adds vector support : Page 2 of 2

October 15, 2020 //By Nick Flaherty
Open source RISC-V reference simulator adds vector support
The open source riscvOVPsim RISC-V reference simulator and model from Imperas adds a test suite for the latest Vector Instruction Extensions

The tests currently achieve over 85% instruction functional coverage which will approach 100% when the vector instruction extensions are ratified by RISC-V International. The test suite can be generated for any of the recent published draft specifications (including 0.8, 0.9, 1.0draft) and compliant vector engine configurations including enhanced options such as use of BFloat16 for floating point optimized for accelerating machine learning and near-sensor computing applications.

The simulator and test suites are freely available with many processor, behavioural, and virtual platform models, with various SystemVerilog examples and test benches for Hardware Design Verification and other community resources from Open Virtual Platforms.

“The RISC-V International working groups have made considerable progress in building a robust ecosystem of tools to help developers more easily test and verify RISC-V solutions,” said Mark Himelstein, CTO of RISC-V International. “We’re pleased to see Imperas’ contributions for this reference model and early RV32I test suite, which really underscore the importance of compliance suite adoption for the whole community.”

“The AndesCore NX27V processor was the first licensable RISC-V core to support the new RISC-V vector instruction extension,” said Charlie Hong-Men Su, CTO and Executive Vice President at Andes Technology Corp. “In addition to Andes' own cycle accurate reference model, Andes has certified the Imperas RISC-V Vectors reference model for use with lead customers and partners with this exciting and powerful new era of compute technology.”

“An architectural validation suite is not a complete verification test plan for a RISC-V processor but shares many similar attributes and its adoption is always useful at any stage of a project,” said Bill McSpadden, Principal VLSI Verification Engineer at Seagate Technology, and co-chair of the RISC-V International's Technical Committee task group for compliance. “Any test plan requires four items – a device to test, some tests, a reference to compare against and a test plan. An easy-to-configure reference model that supports coverage driven analysis, like Imperas' riscvOVPsim, is central to any test plan.”

“RISC-V Vectors Extensions are not just a technical specification, they represent the framework to develop the next generation of compute engines for key markets with advanced requirements,” said Simon Davidmann, CEO at Imperas. “The dynamic multi-state operation of a vector processor is not just complex to design but is pushing the boundary of state-of-the-art design verification methodologies. Imperas simulation technology and reference models are now at the centre of the most advanced design verification teams adopting RISC-V.”

The free riscvOVPsim is now available on GitHub while the free enhanced riscvOVPsim including the vector test suite is now available on OVPworld.

www.imperas.com

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