The package is designed to provide developers with comprehensive support for the Western Digital SweRV Core EH1, a production-grade RISC-V core developed by Western Digital Corp. last year and currently supported and available to the open-source community through CHIPS Alliance , an open-source development organization which seeks to provide a barrier-free environment to allow collaboration for open-source software and hardware code.
The SweRV Core EH1 is a 32-bit, 2-way superscalar, 9-stage pipeline core with performance of up to 4.9 CoreMark/MHz and a small footprint, with clock speeds of up to 0.8 GHz on a 28nm CMOS process technology. The first of Western Digital’s RISC-V-based SweRV Core family, it is intended for use in embedded devices that support high-performance applications.
The SweRV Support Package (SSP) , developed by Codasip in cooperation with Western Digital, provides a comprehensive set of tools and components needed to design, implement, test, and write software for a SweRV Core-based system-on-chip, integrated into one smart ready-to-use working environment. Support for leading EDA flows, from open source to commercial, models and examples, documentation, are all included and backed by professional technical support.
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