We had alluded earlier to Samsung’ FinFET transistor being much longer than the stated process node. They are not alone in this as both Intel, and TSMC sport finFET gate lengths longer than the process node (Table 1 below). In fact, there is not much in the way of lithographic sizes that are the same as the declared process node. How can this be?
Table 1: Selected Transistor Dimensions for Samsung, Intel and TSMC
||Samsung 14 nm
||Intel 14 nm
||TSMC 16 nm
|Fin pitch (nm)
|1/3 fin pitch
|Contacted gate pitch (nm)
|Minimum metal pitch (nm)
|6T SRAM cell area (µm2)
Figure 5 provides a clue. We have plotted both the physical gate length that we have measured for a number of advanced logic devices vs. the manufacture’s claim process node, along with the contacted gate pitch of the transistors. Transistors fabricated at the 130 nm process node and larger exhibit gate lengths that about the same as the process node. But from about the 110 nm down to the 65 nm node, the gate lengths shrink faster than the process node, being shorter than the process node. The rate of gate length shrinkage has slowed for the 45 nm and smaller process nodes.
We have also plotted the contacted gate pitch for the same devices, and this pitch is about 3.3 times that of the process node, and is consistent for all of the process nodes. We also find that the minimum metal pitch also scales as approximately 3X process node.
We often use the contacted gate pitch and 6T SRAM cell area as proxies for the process node; which raises questions as to whether a claimed 16 nm or 14 nm process node is really the node. For example, Samsung’s fin pitch, gate length, contacted gate pitch and 6T SRAM cell are all larger than Intel’s 14 nm process, and its 6T SRAM cell area is bigger than TSMC’s 16 nm SRAM. So is it really a 14 nm process?
One of our engineers has suggested that the fin pitch is a proxy for the process node, much like we see with the active pitch in DRAMs and STI pitches in NAND flash memories. We list the 1/3 fin pitch in Table 1 for the Intel, Samsung and TSMC 16/14 nm node devices, and indeed this is not a bad proxy for the process node.
Figure 5: Transistor Gate Length and Contacted Gate Pitch vs. Process Node (Source: TechInsights)
What should we expect for their 14 nm Low Power Plus (LPP) process? Samsung’s recent press releases suggest that the LPP process will feature a 15% increase in the transistor switching speed and a 15% power consumption decrease. These are being achieved by increasing the transistor’s fin height and enhanced strain engineering. For me, I am anticipating a bit of a process shrink as well to bring the transistor and 6T SRAM cell sizes closer to that of Intel.
For now, we will bide our time until the Exynos 8 SoC or Snapdragon 820 SoC are released in the next generation of Apple and Samsung Smartphones.
About the author:
Kevin Gibb, Product Line Manager, TechInsights.