Siemens certifies tools for TSMC 3nm process, boosts cloud, 3D chiplet tools

October 27, 2021 // By Nick Flaherty
Siemens certifies tools for TSMC 3nm process, boosts cloud, 3D chiplet tools
Siemens EDA has reached key milestones for cloud-enabled chip design at leading process nodes and 3D silicon stacking with foundry TSMC

Siemens EDA tools have been certified for TSMC’s N3 and N4 processes include the Calibre nmPlatform for physical verification and IC sign-off, as well as the Analog FastSPICE Platform, which provides leading-edge circuit verification for nanometer analog, radio frequency (RF), mixed-signal, memory, and custom digital circuits.

The Calibre tools have been used by a leading design house in a cloud computing environment, following the industry trend of moving EDA tools to the cloud to provide more scaling.

Siemens and TSMC have also been working closely on advanced process certifications for the Aprisa place-and-route tool for the most advanced processes. Calibre is being used by leading design house GUC in Taiwan for 3nm designs.  

“TSMC continues to develop innovative silicon processes that enable our mutual customers to bring to market many of the world’s most advanced ICs,” said Joe Sawicki, executive vice president, IC-EDA for Siemens Digital Industries Software.  “Siemens is proud to collaborate with TSMC to continue to deliver difference-making technologies that enable our mutual customers to deliver IC innovations to market more quickly.”

Siemens EDA has also completed the design requirements for TSMC’s 3DFabric design flows. As part of the qualification process, Siemens enhanced its Xpedition Package Designer (xPD) tool to support Integrated Fan-Out Wafer Level Packaging (InFO) design-rule handling with automated avoidance and correction. Calibre 3DSTACK, DRC and LVS are furthermore enabled and certified for the latest TSMC 3DFabric technologies, including InFO, CoWoS, and TSMC-SoIC.

This translates into shorter design and signoff cycles with fewer errors associated with manual interventions. 

Siemens has also built a Design for Testability (DFT) flow for TSMC’s 3D silicon stacking architecture using its Tessent software. This provides a leading-edge DFT solution based on hierarchical DFT, SSN (Streaming Scan Network), enhanced TAPs (test

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