Single Wire Aggregation IP for FPGAs

September 10, 2020 //By Nick Flaherty
Single Wire Aggregation IP for FPGAs
Single Wire Aggregation (SWA) IP for Lattice FPGAs consolidates data links into a single connection between embedded boards

Lattice Semiconductor has develop IP for Single Wire Aggregation (SWA) in its FPGAs to reduce the reduce overall system size and BOM cost in industrial, consumer, and computing applications.

The IP allows developers to use the Lattice FPGAs to reduce the number of board-to-board and component-to-component connectors in their embedded designs,  increasing reliability and reducing overall system footprint and cost.

Connectors used to link circuit boards and modules in electronic systems can be costly, take up valuable space in devices with tight form factors, and over time can degrade and negatively impact system reliability. Routing signals between multiple connectors on space-constrained circuit boards can also create design challenges that increase overall time-to-market.

The IP can be used to aggregate I 2C, I 2S, UART and GPIO data lines into an iCE40 UltraPlus FPGA with a single wire interface without the need for HDL programming.

“Developers are always looking for innovative ways to simplify and accelerate the development of embedded systems, while still maintaining the lowest BOM cost possible. Our new SWA solution meets all three of these needs by reducing the number of connectors in a system,” said Hussein Osman, Market Segment Manager at Lattice.

“The solution is a strong fit for both novice and expert FPGA developers. Its pre-configured bitstreams help those new to FPGA-based design quickly configure an SWA application without requiring HDL coding experience, while the solution’s support for expanded parameterization makes it easy for FPGA experts to combine the Lattice SWA bitstreams with their own HDL code,” he said.

Lattice currently offers several aggregated I/O configurations in pre-configured bitstreams for fast application prototyping, including two I 2S, an I 2C peripheral, an I 2C controller, and eight GPIO signals, or six I 2C controller and two GPIO signals. It also aggregates one I 2C controller and 12 GPIO signals, three I 2C controllers, two I 2C peripheral, and

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