Software-defined processor startup selects UltraSoC IP

May 24, 2020 // By Peter Clarke
Software-defined processor startup selects UltraSoC IP
SimpleMachines Inc., a startup spun out of the University of Wisconsin at Madison in 2016, has opted to make use of embedded analytics IP from UltraSoC Ltd. for its forthcoming Composable Computing Platform silicon.

SimpleMachines' approach to computing in the datacenter is in essence that hardware should be malleable and conform to software requirements. The implication is that there is a benefit to simplifying and slowing the hardware down to allow for rapid reconfiguration.

The Composable Computing Platform is somewhat akin to a reconfigurable FPGA. The software API, compiler and hardware implementation analyse a program's properties in terms of shape, size and data requirements. The software stack transforms the layout of the processor's storage and execution units on-the-fly to match the data and computation patterns.

The technology has been applied to convolutional neural networks, long short-term memory recurrent neural networks, transformers, and regression trees.

UltraSoC's embedded analytics are being designed into SiliconMachine's processors allowing monitoring of internal bus transactions, processor execution and other system-wide behaviors within the device.

This allows performance of a custom chip built for that application, in a multitude of circumstances. Reconfiguration is described as taking milliseconds, which does represent thousands of clock cycles.

The software around the reconfigurable processor identifies four fundamental behaviors: data-fetch, synchronization, computation, and control. Once identified, the chip directly implements the four behaviors at the basic level of a tile. The processor integrates 128 such tiles interconnected with an on-chip network. A dynamic runtime engine provides an abstraction of thousands of such tiles and in effect, performs the layout and synthesis tasks that an ASIC designer would have taken months to complete for a single custom chip.

The compiler has been designed to integrate into the backends of the popular machine learning development environments TensorFlow, ONNX, and PyTorch.

The company was founded by Karu Sankaralingam, an associate professor of computer science at the University of Wisconsin–Madison, in 2016 and raised $2.9 million in seed funding in 2017. In 2018 Baidu Ventures and IMO Ventures contributed to a $16.7 millon Series A round of equity funding.

Simulation tools, emulation tools, an SDK, and a limited number of FPGA trial cards are

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