SOI group moves on mobile front

February 11, 2011 // By Mark LaPedus
SOI group moves on mobile front
Jockeying for position in the next-generation transistor race, the SOI Industry Consortium claims to have made more progress in bringing fully-depleted silicon-on-insulator (FD-SOI) technology for next-generation mobile products.

The consortium members-ARM, Globalfoundries, IBM, STMicroelectronics, Soitec, and CEA-Leti—have announced results of an assessment and characterization of FD-SOI, saying that the technology is viable for mobile and consumer devices at the 20-nm node and perhaps beyond. The group has demonstrated the benefits of planar FD-SOI technology for these applications based on an ARM processor.

FD-SOI is one of several options competing for the next-generation transistor structure. At present, leading-edge chip makers are using conventional bulk CMOS and planar transistor structures for the 32-/28-nm nodes.

AMD, IBM and others are also using another type of SOI technology-partially depleted SOI-for their respective processors. In contrast, Intel Corp. has dismissed SOI, saying that it does not require the technology.

For 22- and 16-nm, there are a number of transistor candidates on the table: III-V, bulk CMOS, FinFET, FD-SOI, multi-gate, among others. So far, there are no clear winners.

Mark Bohr, Intel Senior Fellow and director of process architecture and integration at Intel Corp., recently said the chip giant is evaluating extremely-thin SOI, sometimes called FD-SOI. One source even thinks Intel is looking at rival tri-gate structures at 22- or at 15-nm. Bohr declined to elaborate on Intel’s directions.

In a recent interview, Gary Patton, vice president of the Semiconductor Research and Development Center at IBM Corp., said FD-SOI is a strong candidate for the 22-nm node. Some of the big silicon foundries-Globalfoundries, Samsung and TSMC-have dropped hints that they will push bulk CMOS silicon for the 20-nm node due to cost.

But many high-performance applications may also require FD-SOI. SOI refers to the use of a layered silicon-insulator-silicon substrate in IC manufacturing, which is said to reduce parasitic device capacitance and improve performance.

In FD-SOI, the top silicon layer is between 5- to 20-nm thick. ''Silicon under the gate is so thin that it is fully depleted of mobile charges,’’ according to Soitec, in a newsletter. ''There is no floating body effect.’’

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