SoM is built around multi-core RISC-V SoC FPGA

January 29, 2020 // By Julien Happich
The M100PFS SoM developed by Aries Embedded is based on the PolarFire SoC, Microchip’s SoC FPGA family that combines a high-performance 64-bit RISC-V multicore processor subsystem with low-power FPGA technology.

Well suited for secure, power-efficient computation in a wide range of applications, the 74x42mm M100PFS SoM runs with low device static power, low inrush current and low-power transceivers. The PolarFire FPGA technology stands out for its reliability with single-event upset (SEU) immunity, built-in SECDED and LSRAM memory interleaving built into the FPGA fabric. In addition, SECDED runs on all processor memory resources and the system controller suspend mode serves safety-critical designs. Several features support security aspects: for example, Cryptography Research Incorporated (CRI)-patented differential power analysis (DPA) bit stream protection, integrated dual physically unclonable function (PUF), and 56 KB of secure, non-volatile memory (sNVM).
The PolarFire SoC onboard the M100PFS SoM from ARIES Embedded combines a Quad 64-bit RISC-V 64GC core and a 64-bit RISC-V 64 IMAC monitor core. The SoM uses the FCVG484 package that scales from the PolarFire SoC’s 23k logic element (LE) device up to the 250k LE device. A SoM offering the largest 460k LE PolarFire SoC device will be offered in later versions. The RISC-V CPU micro-architecture implementation is a simple 5-stage, single issue, in-order pipeline that is immune to the Meltdown and Spectre exploits found in common out-of-order machines. All five CPU cores are coherent, with the memory subsystem allowing a versatile mix of deterministic real-time systems and Linux in a single multi-core CPU cluster.

Aries –

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