European design house Sondrel has taped out of its largest chip design for a customer.
The 500 square millimetre chip has over 30 billion transistors with 23 thousand pads for I/O, power and ground linked to pads on the underside and took a team of 200 engineers.
“This initially started out as a design for 28nm technology,” explained Stuart Vernon, Sondrel’s Senior Director of Physical Design. “However, it soon became apparent that, on 28nm, it would either be one very big chip, which would not have been cost effective, or it would have to be be split into two connected chips, which would introduce parasitics and timing issues. So the decision was made to use the 16nm TSMC process node to enable the design to fit onto a single chip at a cost effective price point.”
Around a third of the floor plan of the chip is the block with the customer’s IP that handles the real-time image processing. Sondrel wrapped round that support blocks of Graphical Processor Unit, two Central Processor Units, on-chip cache memory, PCI and USB interfaces plus memory controllers to off-chip memory using over 7 kilometres of metal tracks on a chip the size of a postage stamp.
The chip has 300 million placeable logic cells and the placement tool can only handle 3 million at a time without the runtime becoming excessive. It was therefore divided into manageable-sized, functional blocks over four levels of a hierarchy structured like a pyramid. This enabled the design of the blocks to be divided between Sondrel teams that are located around the world. Once each block was finished, the big challenge was to bring them all together by creating abstract models of the lower blocks to provide input for the higher blocks so that the size of the part of design being implemented remained manageable. As the chip can run at up to 100W, the heat output of the different parts