The concept is manufacturing-friendly on 300mm wafers using CMOS-compatible processes and does not compromise the reliability and sub-ns writing performance of the SOT-MRAM devices, claims imec, opening possibilities for the development of future MRAM-based technologies and non-volatile logic and memory applications.
Thanks to a high endurance and sub-ns switching speed, the new SOT-MRAM devices could potentially replace fast L1/L2 SRAM cache memories. Writing of the memory elements is performed by injecting an in-plane current in a SOT layer that is adjacent to a magnetic tunnel junction (MTJ). During write operation, a small in-plane magnetic field is required to break symmetry and ensure deterministic magnetization switching. In today’s devices, this is done by applying an external magnetic field, which is recognized as a major hurdle for the practical use of these devices.
Instead, imec’s ‘field-free’ switching concept consists in embedding a ferromagnet in the hardmask that is used to shape the SOT layer. With this ferromagnet, a small homogeneous in-plane field is induced on the free layer of the magnetic tunnel junction.