Standard cell IP library offers 20% silicon area savings for volume logic ICs

July 27, 2016 // By Graham Prophet
Standard cell IP library offers 20% silicon area savings for volume logic ICs
For integrated circuits that are to be produced in very high volumes, such as microcontrollers, SESAME uHD (ultra High Density), the flagship product in Dolphin Integration's standard cell library offering, can provide a route to decreasing die costs.

The library employs IP vendor Dophin’s patented pulsed latches as “Spinner Cells” instead of standard D-flip flops, documented in “ Thorough validation: the conundrum of Pulsed latch libraries turned practical as Spinner systems ”, which deliver optimised low-power consumption.

Using this alternative technology, together with its industrialized package fully supported with scripts and manuals, users can save up to 20% silicon area on logic blocks, depending on the targeted frequency and the selected threshold voltage.

The chart shows the technology applied to the public benchmark Motu Uta V5, using 7 metal layers. Palce & route was performed with multi-corner and multi-mode at nominal voltage. The public Motu-Uta benchmark allows the straightforward comparative evaluation of SESAME uHD with other standard cell libraries, showing its benefit immediately.

Available from 180 nm to 40 nm (foundry sponsored at TSMC 55 nm LP-eFlash) and compatible both with Cadence and Synopsys EDA solutions, SESAME uHD supports Dual voltage to benefit from Low voltage and multiple threshold voltages (HVT, SVT, LVT), which enables users to take advantage of many configurations.

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