Synopsys has deployed its IC Validator physical verification design tools on Samsung's SAFE EDA Cloud Design Platform (SAFE-CDP). This collaboration enables designers targeting Samsung Foundry advanced process nodes to achieve significant compute resource savings of up to 30 percent and faster signoff.
Mutual customers of Synopsys and Samsung Foundry can use the IC Validator tools and Samsung Foundry process technology on the SAFE CDP platform which is powered by cloud hardware from Rescale and Microsoft Azure.
"Turnaround time for physical verification has become critical at advanced nodes and our mutual customers need a cloud-based solution to accelerate physical verification productivity and overall design closure," said Sangyun Kim, vice president of Foundry Design Technology Team at Samsung Electronics. "Synopsys IC Validator is optimized for on-demand physical signoff on Samsung SAFE Cloud Design platform, delivering significantly improved turnaround time and efficient resource usage."
"Rescale is proud to provide the HPC infrastructure that powers the SAFE platform for fabless design in the cloud," said Joris Poort, CEO of Rescale. "We share Samsung's vision that the cloud can accelerate product innovation and provide superior usability and economics across so many EDA workflows, and we're very excited to see that Synopsys brought its leading physical verification solution to Samsung SAFE, giving designers an on-demand access to HPC cloud computing to accelerate physical signoff and significantly reduce compute resources costs."
IC Validator includes design rule checking, layout-versus-schematic, programmable electrical rule checks, dummy metal fill and design-for-manufacturability enhancement capabilities. The tool suite uses memory-aware load scheduling and balancing technologies to scale on cloud hardware with both multi-threading and distributed processing across thousands of CPUs. The elastic CPU technology dynamically assigns and releases CPU resources, delivering optimal resource utilization and reduced compute costs.
"As designers adopt advanced technology nodes, physical verification closure within schedule is becoming a major challenge, and tapeout delays can dramatically impact our customers' product