Tensilica plans 2048bit wide DSP core

April 22, 2021 // By Nick Flaherty
Tensilica plans 2028bit wide DSP core
Cadence has launched the Tensilica Q8 1024bit and Vision P1 128bit SIMD DSP cores for AI processing and is planning a 2048bit version

Cadence Design System has added two new versions of its Tensilica digital signal processing IP core with 1024bit and 128bit versions, and is planning a 2048bit version.

The Q8 is the seventh generation of high end DSP core with a 1024bit wide single instruction, multiple data (SIMD) architecture. The Vision P1 at 128bit SIMD marks the low end. “With these two products we have a portfolio from the low end to high end,” said Pulin Desia, group director of Tensilica Vision and AI product marketing at Cadence.

The Q8 is aimed at vision and AI systems as well as sensor fusion for cameras and lidar for designers using the current 512bit wide Q7 core. The company is planning a 2048bit core. “With the bigger DSPs we like to come out every two years. It depends on the market – we might do some incremental improvements in between,” he told eeNews Europe.

This provides scalability in performance with the same software.

“People want an alternative to ARM, that’s what we see and it’s a new opportunity for us to provide a solution in the market,” said Desia. “People want to put something closer to the sensor and using the N-way SIMD programming model we can move from the low end to high end and maintain the software investment with custom instructions,” he said.

AI has been a key factor in the design, and both DSPs also support Xtensa Neural Network Compiler (XNNC) and the Android Neural Networks API (NNAPI) for neural network support as well as over 1700 OpenCV-based vision library functions, OpenCL and the Halide compiler for computer vision and imaging applications.

Doubling the SIMD width doubles the performance of the Q8 to 3.8TOPS with a 13 stage pipeline but additional multiple accumulate (MAC) blocks provide 4x the AI performance with 20 percent lower power for a single core. Up to four cores can be combined on a chip.   

The Vision P1 DSP with a ten stage pipeline is optimised for always-on applications using AI including smart sensors, AR/VR glasses and IoT/smart home devices with 400GOPS performance. This has one-third the power and area compared to the Vision P6 DSP.

Both cores are automotive ready with ASIL B hardware random faults and ASIL D systematic fault certification.

The Tensilica Vision Q8 DSP is available now, while the Tensilica Vision P1 DSP is expected to be available for general release in the second quarter of 2021.

www.cadence.com

Related DSP articles 

Other articles on eeNews Europe 


Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.