Tessent boosts simultaneous analysis of hardware and software in SoC designs

July 23, 2021 // By Nick Flaherty
Tessent boosts simultaneous analysis of hardware and software in SoC designs
Siemens has revamped UltraSoc’s UltraDevelop2 tools as Tessent SystemInsight integrated development environment (IDE) to support cycle-accurate processor trace and a range of open-source Python implementations for analytics.

Siemens has renamed and upgraded the system on chip hardware and software development tools it acquired with Cambridge startup UltraSoC.

Tessent SystemInsight is based on UltraSoC’s UltraDevelop2 tool as a complete Eclipse-based (IDE) that extends the features of a traditional debugger with run control and trace with support for heterogeneous SoC designs

This provides simultaneous debug of hardware and software as well as remote debug to provide full system visibility when connected to an SoC equipped with Tessent Embedded Analytics, with seamless support for diverse instruction set architectures (ISAs) and manycore designs in one integrated tool. This enables engineers to simultaneously view the behaviour of hardware structures and the execution of software across the entire SoC.

This  helps tackle the challenges of silicon bring-up, validation and debug which can be one of the most time-consuming and costly parts of the silicon development process. Bugs that did not appear during verification can start appearing when hardware, software and system stimuli are brought together in the first runtime environment. Many of these effects are subtle, hampering performance in unexpected ways, while not actually causing the system to become non-functional.

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Tessent SystemInsight tackles this with the Embedded Analytics functional monitoring in the silicon and the SystemInsight IDE on the host side, allowing designers to monitor not just activity at individual cores but also what is happening across the SoC bus fabric. It provides a holistic, system-level approach to SoC development and debug, allowing visibility of the interlinked behaviour of hardware, firmware and software at any level of abstraction.

The tool has been extended beyond the use of Python3 from Anaconda with installations using Python.org, removing any obligation to license Anaconda and allowing the design team to choose the appropriate toolset.

The latest Java Runtime Environment JRE 11 is also bundled inside SystemInsight and the Java code has been updated to support Eclipse 2019-12 (4.14). There is no longer a requirement for Java to be preinstalled to install SystemInsight and if there are no other programs using Java it can even be uninstalled.

Tessent SystemInsight now provides support and visualization for cycle accurate trace delivered off-chip using the latest Embedded Analytics Trace Encoder. This allows developers to see precise, tabulated timing for every instruction traced, even in systems where multiple instructions can be in flight, pending retirement.

As Tessent SystemInsight is target agnostic it will interface to and debug a functional target whether it be simulated, emulated, in FPGA or silicon with remote debug over TCP to allow disitrbuted teams to work on the same target.

resources.sw.siemens.com/en-US/fact-sheet-tessent-systeminsight-for-soc-debug

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