German RISC-V developer Codasip has launched three 64-bit RISC-V application processor cores with multi-core and SIMD single instruction, multipple data capability for higher performance system designs in edge AI.
The A70XP provides support for RISC-V P extensions, and the A70X‑MP and A70XP‑MP enable the creation of symmetric multi-processor (SMP) systems.
The RISC-V P extension consists of 331 instructions which can be divided into groups. The A70XP includes a SIMD unit which executes P extension instructions with single-cycle latency. Multi-cycle instructions are pipelined to allow one to be executed every clock cycle. Applications for this core include audio encoding/decoding, sensor fusion, computer vision as well as machine learning edge AI chips.
The A70X-MP and A70XP-MP cores add multi-core features supporting clusters of up to four cores in an SMP configuration with configurable L1 and L2 caches with a scalable microarchitecture.
The A-series of a application are based on the Bk7 microarchitecture with Floating Point Unit and Atomic instructions and all use the an AXI external interface. They also support Machine, Supervisor & User privilege modes and have a Memory Management Unit to support Linux and can be customised using Codasip Studio.
“We are delighted to extend our range of Codasip RISC-V application processors with cores offering higher performance,” said Karel Masařík, CEO of Codasip. “These new cores are the combined work of our new French Design Centre and our main R&D Centre in Brno.”
The three cores will be available in the first quarter of 2021.
Alongside the A-series Codasip is creating two processor families for the embedded domain with a L-series for low power embedded based on the Bk3 core and the H-series for High Performance embedded designs based on the Bk5.
Related RISC-V articles
- CODASIP OPENS DESIGN CENTRE FOR THE ISA IN FRANCE
- IMAGINATION LAUNCHES FULL COURSE FOR THE ARCHITECTURE
- CLOUD-BASED RTL TOOL FOR THE CORES
- CODASIP SUPPORTS THE WESTERN DIGITAL SWERV EH2 & EL2 CORES