Control of a multicore system and debugging is carried out with the UDE 4.2 in a consistently designed user interface. Various colors determinable by the user and user-definable groups of views for individual function units ensure a fast overview and simple navigation that is needed in complex SoC developments. Individual cores can be specifically selected and also synchronized for control by the debugger. This also includes the extensive use of existing on-chip trigger and synchronization options of various device manufacturers. With the UDE 4.2, the consistent user interface ensures the greatest possible flexibility when controlling a multicore target, without the need to know the underlying on-chip logic in detail.
The trace framework of the Universal Debug Engine 4.2 has also been equipped with numerous new features. For example, relocation of the data processing in a separate process not only increases the speed of the evaluation, but also allows persistent storage of trace sessions for analysis at a later time without direct access to the target. Furthermore, comprehensive filters and the possibility to individually color recorded events of various trace sources simplify a clear presentation of the results.
An enhancement of the proven Universal Emulation Configurator (UEC) of the Universal Debug Engine (UDE) ensures an even more efficient use of the emulation devices offered by Infineon, Freescale and STMicroelectronics for some SoCs. Programming of the additional trigger logic contained on the emulation devices is performed by a graphical configuration of trace tasks, by which signals and actions are linked via a state machine.
With PLS’ Universal Access Device 3+ (UAD3+) , a powerful hardware tool with 4 GB external trace memory is available for recording trace data. Thanks to an Aurora trace pod supporting four serial high-speed lanes each with 3.25 gigabit per second (Gbit/s) transfer rate and a parallel trace pod for recording signals up to 500 MHz, the UAD3+ is also well equipped to meet future requirements.