EUV will be key to 2nm and below, says Mii. “Looking forward we plan to use new masks and materials, new resists and multiple patterning,” he said. “This will enable patterning well beyond N2 (2nm). We are also working with ASML for scanners with a high numerical aperture (NA).”
These technologies will be developed at a new R&D centre. “The first phase started in Q1 and is expected to be completed in 2021 and will house 8000 scientists and engineers,” said Mii.
TSMC has also launched a 4nm process, N4, as a shrink of the current N5 process that is compatible with the current IP and SPICE models but with less masks and higher logic density for a smaller die size to reduce the cost.
- FIRST SEVEN CUSTOMERS FOR 5nm TSMC PRODUCTION
- NXP, TSMC TEAM ON 5nm AUTOMOTIVE PROCESS
- TOP TEN CHIP FOUNDRY REVENUES SEE BOOST
Other articles on eeNews Europe