UltraLink D2D PHY IP supports die-to-die connectivity

November 14, 2019 //By Julien Happich
PHY IP
Cadence Design Systems’ UltraLink D2D PHY IP is a low-latency PHY for die-to-die connectivity targeted at the AI/ML, 5G, cloud computing and networking market segments.

The new IP was designed as an enabling technology for chiplet and system-in-package (SiP) applications, for SoC providers to deliver more customized solutions while also shortening development cycles. The UltraLink D2D PHY IP delivers up to 40Gbps wire speed in an NRZ serial interface, providing up to 1Tbps/mm unidirectional bandwidth. The IP includes built-in de-skew and scrambling/de-scrambling logic to enable easy system integration. Its low wire count of 28 data wires for 1Tbps bandwidth enables easier routing and potentially reduces package cost, whereas alternative solutions can require 30% or more wires. While some existing lower speed die-to-die solutions require a silicon interposer to achieve the same bandwidth, the UltraLink D2D PHY IP offers significant cost advantages by supporting multi-chip modules on organic substrates. This IP features latency as low as 5ns round trip from receiver to transmitter, utilizes standard non-return-to zero (NRZ) coding and achieves better than 10-15 bit error rate (BER) without requiring forward error correction (FEC). The UltraLink D2D PHY IP is silicon proven in an advanced 7nm FinFET process.

Cadence – www.cadence.com


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