Ultrasoc cores provide 'bare-metal' security

December 01, 2015 //By Peter Clarke
Ultrasoc cores provide 'bare-metal' security
Ultrasoc Technologies Ltd. (Cambridge, England), a provider of debug hardware support cores for multiprocessor embedded systems, is moving into active functionality by providing support for "bare-metal" security.

"Debug is a valuable thing but we realized you can do a lot of other things with the analytical cores we provide," Rupert Baines, the company's CEO, told eeNews Europe.

"For example our on-chip debug support is dynamically aware of what cores are in use and what cores are not." While the activities that Ultrasoc could support on-chip are diverse – including dynamic voltage and frequency scaling (DVFS) to achieve power savings – the first chosen activity is security.

The Internet of Things and the connected car in automotive are expected to be the initial applications for the technology.

The Ultrasoc support hardware is able to monitor accesses to different regions of memory and raise flags if a process enters a forbidden region, it can monitor software behavior patterns and code sequences. Most security is provided above the level of the operating system, said Baines, but this is complementary "bare-metal security" that is non-intrusive and remains robust even if conventional security measures are compromised, he added.

This functionality is provided by the same set of gates that have established benefits for developing an SoC and includes that benefit of supporting multiprocessor and heterogeneous systems. "It's another use case for the same gates, although there will be an incremental license fee and royalty for using the bare-metal security features," Baines added. 

Ultrasoc's debug support comes as a tool box with up to about 30 different debug functions supported by a number of cores. The typical overhead in terms of gates as a proportion of the total varies between 1 or 2 percent and 7 percent.

By adding the security use case it means the Ultrasoc debug support is functionally active after IC deployment as well as in the design phase pre- and post-silicon implementation. 

Although it functions below and outside of the operating system, the technology also provides a means of communicating with software on the device as part of a

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