“The core idea is we put IP into chips that helps get information out that allows you to optimise software for safety and security,” said Rupert Baines, CEO of Ultrasoc. “The fundamental focus is the embedded silicon IP and that’s where most of our focus has been, but the corollary to that is what do you do with the information. The monitors we have are very smart and configurable so you need a way to get information in to configure them.
“We’ve done a deal with Imperas for their MPD software and libraries so that gives us a truly world class development environment, and we are using TraceAnalyser from Percepio for visualisation. They have a really powerful backend database so you can have gigabytes of data to graph and display that all context sensitive,” he said.
The tools include a library of debug adapters to enable real-time run control of more than 20 processor core architectures from multiple vendors, including Arm, MIPS and RISC-V (as implemented by Andes, Esperanto and SiFive), amongst others
“We have expanded the RTOS tracing to hardware and software states with all of the semantics and linkages built in and we’ve made it very extensible – there’s an Eclipse framework TCS for plug ins and a link to Python so users can automatically script tests and verification,” he said.
A key addition is hooks for machine learning and data science analytics such as automated anomaly detection, hat mapping and root cause analysis. “This is very much a framework, so talking to our IP in the hardware is exclusively us, but interacting with the outside world is very much plug in and standards based,” said Baines.
Next: Moving into system level monitoring