Understanding DDR SDRAM timing parameters: Page 3 of 4

June 25, 2012 // By Deepak Kumar, Sumit Varshney, Sunaina Srivastava and Swapnil Tiwari
Understanding DDR SDRAM timing parameters
Many an engineers who have ever dealt with DDR SDRAM must have been intrigued by the various timing parameters of the DRAM. This article explains the various timing parameters and its impact on the performance of the DRAM.

available until a few clock cycles later, because the memory is pipelined. When an access is requested to another row, the current row has to be deactivated by issuing the "precharge" command. The precharge command takes a few clock cycles before a new "active" command can be issued.

Now we can study the detailed definition of various timing parameters.

CAS Latency (CL) : CAS Latency (Column Access Strobe Latency), also known as “Access Time”, is the most important memory parameter and is the first of the series of numbers. It is the delay time between the moment a memory controller tells the memory module to access a particular memory column on a RAM memory module, and the moment the data from given array location is available on the module's output pins. In DDR SDRAM it is specified in clock cycles, while in asynchronous DRAM it is specified in nanoseconds.

RAS to CAS Delay (tRCD): ‘tRCD’ stands for row address to column address delay time. Inside the memory, the process of accessing the stored data is accomplished by first activating the row then the column where it is located. tRCD is the time required between the memory controller asserting a row address strobe (RAS), and then asserting a column address strobe (CAS) during the subsequent read or write command. The lesser this time, the better it is, as the data will be read sooner.

RAS Precharge (tRP): Whenever a new row is to be activated for the purpose of accessing a data bit, a command called “Precharge” needs to be issued to close the already activated row. RAS Precharge time, tRP is the number of clock cycles needed to terminate access to an open row of memory, and open access to the next row.

Active to Precharge Delay (tRAS): After an “Active” command is issued, another “Precharge” command cannot be issued until tRAS has elapsed. So, tRAS is the minimum


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