Update: IMEC, Cadence tape out first 5nm test chip

October 07, 2015 //By Peter Clarke
Update: IMEC, Cadence tape out first 5nm test chip
Nanoelectronics research center IMEC and EDA company Cadence Design Systems Inc. have announced that they have completed the first tape out of a test chip to be built using a 5nm manufacturing process.

The tape out is aimed at a process that includes both extreme ultraviolet (EUV) lithography as well as 193nm immersion lithography.

There are no active devices in the tape out, which is just back-end-of-line patterning for metal 2 and metal 3 and the cuts, links and via structures between them. The target transistor is a FinFET and the M2 and M3 information is derived from a full processor design, although the front-end-of-line is not included in the tape out.

Place and Route of the M2 layer. Source: IMEC.

IMEC and Cadence are using a mix of self-aligned quadruple patterning and EUV lithography. Metal pitches were scaled from the nominal 32nm pitch to 24nm pitch to push the limit of patterning. The two parties did not declare which processor was used but such designs are often done with a Cortex-A series processor that is well-characterized at previous node.

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